In a system in package (SiP) that is one of package technologies of a semiconductor device, a plurality of semiconductor chips are stored in a single package. I/O (input/output) terminals of the plurality of semiconductor chips, which are stacked in SiP, are joined to each other by a bump such as a microbump and the like. In a semiconductor device in which the plurality of semiconductor chips are stacked, there is a possibility that a failure may occur in a signal path including the I/O terminals, the microbump, and the like due to a manufacturing defect of the microbump, and the like. For example, a failure in which the signal path including the I/O terminals, the microbump, and the like enters an open state, a failure in which interconnections adjacent to each other are short-circuited, and the like occur. There is suggested a method in which two semiconductor chips are connected to each other through a bump, and then a connection state of the semiconductor chips is tested so as to detect the failure in the signal path of the semiconductor chips which are stacked (for example, refer to Japanese Laid-open Patent Publication No. 2004-317352).
In addition, a decrease in a yield ratio (yield ratio of the semiconductor chips) due to a joining defect at the microbump becomes a cause for increasing the cost of SiP. So as to suppress an increase in the cost of SiP, with regard to the semiconductor device in which the plurality of semiconductor chip are stacked, there is suggested a technology of relieving the defect by bypassing a failure site (for example, refer to Japanese Laid-open Patent Publication Nos. 2011-81887, 2013-105996, and 2003-309183).
Detection of the failure site in the signal path between the semiconductor chips is carried out by using a scan flip-flop that is provided in correspondence with each terminal that is an inspection target, and the like. The scan flip-flop is a flip-flop circuit corresponding to a scan test, and operates in synchronization with a clock for test (hereinafter, also referred to as a test clock). A test circuit that is embedded in a semiconductor device operates in synchronization with the test clock, and sets test data in the scan flip-flip on one side of the semiconductor chips, which are connected to each other, through a scan chain and the like.
In addition, the test circuit transmits test data from the scan flip-flop on one side of the semiconductor chips which are connected to each other to the scan flip-flop on the other side. According to this, the test data is retained in the scan flip-fop of the semiconductor chip on the other side. In addition, the test circuit acquires the test data that is retained in the scan flip-flop of the semiconductor chip on the other side through the scan chain and the like, and detects a failure site in the signal path between the semiconductor chips based on the data that is acquired.
In addition, there is suggested a data retaining circuit in which the flip-flop circuit is made redundant to reduce an effect of malfunction of the flip-flop circuit (for example, refer to Japanese Laid-open Patent Publication No. 2002-185309). For example, this kind of data retaining circuit retains input data in three flip-flop circuits, and outputs data in accordance with a logical value which occupies the half or greater among a plurality of pieces of output data of the three flip-flop circuit. In addition, with regard to a semiconductor integrated circuit that is manufactured by using a silicon on insulator (SOI) technology, there is suggested a configuration in which a test circuit is made redundant (for example, refer to Japanese Laid-open Patent Publication No. 62-169355).
In signal paths between the semiconductor chips which are connected to each other, a failure may occur in a signal path (hereinafter, also referred to as a clock path) of the test clock. In this case, it is difficult to operate the scan flip-flop and the like, and thus it is difficult to carry out a test for detecting a failure site in the signal path between the semiconductor chips. That is, in a case where a failure occurs in the clock path among signal paths between the semiconductor chips which are connected to each other, it is difficult to retrieve the failure by bypassing a failure site. As a result, a yield ratio of the semiconductor device decreases, and thus the manufacturing cost of the semiconductor device increases.
According to an aspect, an object of the test circuit and the method of controlling the test circuit according to the disclosure is to improve the yield ratio of the semiconductor device.